1. Technical Field of the Invention
The present invention relates to instruction processing by a microprocessor, and more particularly, to the processing of interrupts by a microprocessor.
2. Description of Related Art
Within most microprocessors, such as micro-controllers, digital signal processors, embedded CPUs, etc., the processing of a current task (instruction set) may be stopped to enable the execution of another task related to the current task in response to some external event. The external event is commonly called an interrupt to the microprocessor. The interrupt causes the microprocessor to branch to and begin processing an interrupt service routine consisting of a number of interrupt instructions. After completion of processing of the interrupt service routine, the processor switches back to the original task and resumes processing at the point that it was interrupted.
Processors usually employ a so called pipeline structure for the execution of an instruction set defining a task. A pipeline structure refers to the division of the execution of each instruction into several stages. These stages normally comprise a fetch, decode and execute stage. The fetch stage involves retrieving the instruction from memory for execution. The decode stage involves interpreting the instruction to decide what actions are to be taken, and the execution stage involves actually executing the determined actions.
Currently used methods for processing interrupts to a processor involve branching to a location in memory where the interrupt service routine is stored. Once execution of the interrupt service routine has been completed, a branch returns processing back to where the interrupt stopped processing on the previous task. Unfortunately, the process of branching to the set of instructions defining the interrupt service routine requires the use of overhead to process the interrupt. Overhead involves the execution of clock cycles by the processor where no instructions are actually executed. The branching process requires the execution of two unused clock cycles until the first instruction of the interrupt service routine is executed. Likewise, an overhead of two clock cycles is required to branch back from the interrupt service routine to the original instruction set. Thus, a total of four clock cycles would remain unused upon the execution of each interrupt service routine. If actual processing of the interrupt service routine required only one clock cycle (a single instruction) the overhead would be 400%. Thus, some means of more efficiently processing interrupt service routines that limits overhead generated by the procedure would greatly improve the utilization of processing resources.
Another disadvantage of current systems arises from the fixed location of the code needed to execute a specific interrupt service routine. If different actions must be taken for a specific interrupt service routine depending on when the interrupt is received, the program must introduce "if-then-else" portions within the interrupt service routine code or must change the contents of the program memory for the interrupt service routine to ensure a return to the correct location. The introduction of "if-then-else" portions wastes clock cycles and memory and is thus an unacceptable solution. The changing of the contents of the program memory is a risky and impracticable solution. The fixed locations in memory of the interrupt service routines also means that if one interrupt does not require all of the space reserved in memory for that interrupt, other interrupts may not utilize the unused memory. Thus, means for more efficiently utilizing the available memory resources within a processor with respect to interrupt service routines is also needed.